Introducing a novel neuromorphic, data-flow-based computing architecture
Inspired by the energy efficiency and parallel processing capacity of the human brain.
Data Driven
True Parallelism
Problems must be decomposed into many independent subproblems that can execute simultaneously, enabling exponential—not merely linear—performance gains.
Next-gen
Data-Flow Architecture
Instead of the traditional “fetch-and-store” model, data must flow directly through computation. Eliminating repeated transfers between memory and compute removes the memory wall and unlocks significantly higher throughput.
Mesh Semi NPU
Overview of the Innovation:
The Mesh Semi NPU introduces a novel neuromorphic, data-flow-based computing architecture designed for general-purpose silicon implementation.
Unlike traditional processors, the Mesh Semi NPU:
Operates asynchronously
Eliminates central control units
Propagates both code and data through a symmetric computational matrix
Avoids reliance on clock-driven instruction sequencing
Dynamically configures routing and operations during execution
The architecture is implemented in FPGA for prototyping, and early small-scale implementations have already been developed and tested.
FPGA
Eliminates Central Control
Dynamically Configured
Core Architectural Characteristics
Neuromorphic Design
Inspired by the energy efficiency and parallel processing capacity of the human brain, the NPU uses a connective matrix of dynamically routed nodes. Neural pathways are established during execution, allowing adaptive learning and in situ reconfiguration. This dynamic plasticity positions the NPU as a step toward practical generalized learning systems.
2. True Data-Flow Processing
Unlike Von Neumann systems, which separate memory and compute, the NPU integrates them within the same fabric. Code and data propagate through the matrix, eliminating costly memory transfers. There is no centralized scheduler. Routing decisions occur locally and dynamically.
3. Asynchronous Execution
The NPU differs from systolic arrays (such as those used in TPUs) by removing the clock-driven processing model. Computation propagates asynchronously and is regulated through impedance gating. This eliminates clock idle power, reduces synchronization overhead, and enables higher energy efficiency.
NPU
Asynchronous
Neuromorphic
A Radical Conclusion
The Mesh Semi NPU changes the rules of AI computing
The Mesh Semi NPU is designed as a general-purpose neuromorphic processor capable of accelerating machine learning workloads while remaining adaptable to future algorithmic advances.